The present invention relates to an integrated memory with memory cells which are disposed in at least a first and second memory cell block, in which the memory cells can respectively be read out through a read amplifier and a data line connected to the read amplifier, each memory cell block being assigned at least one dedicated data line, and also to a method of operating such a memory.
Integrated memories often have memory cells in a plurality of separate, identical memory cell blocks. The memory cells are normally disposed at crossing points of word lines and bit lines, being connected in each case to one of the word lines to select one of the memory cells and to one of the bit lines.
During an access to one of the memory cells, generally the relevant word line is selected through a decoder. After the relevant word line has been selected, data signals from the memory cells along the word line are present on the corresponding bit lines. A data signal from a selected memory cell is assessed in a read amplifier of the relevant memory cell block, is amplified, and is read out through a data line associated with the memory cell block. If a memory has a plurality of separate memory cell blocks, for example, in the form of memory banks, as they are referred, the procedures described are normally carried out separately in each case for each of the memory banks.
For test operation of a memory, it is usual to write the same item of information into a plurality of memory cells and read it out again, the data read out being compared with reference data. As a result, it is possible, in particular, to determine whether or not tested memory cells are faulty. For such a purpose, provision is made, for example, of a comparison circuit belonging to the memory, by which data read out can be compared with reference data.
In particular, during test operation of a memory, in which the same item of information is written into a plurality of memory cells and read out again, there is a considerable saving in time as compared with the normal operation of the memory if memory cells of a plurality of memory banks are written with the same data in parallel for one memory cell access during an access cycle. For such a purpose, it is, in particular, necessary to activate a plurality of memory banks or their read amplifiers in parallel (multi-bank activation, as it is referred). A similar procedure when reading out test data is problematic because the test data from the different memory banks cannot generally be compared with reference data in parallel in a comparison register.
It is accordingly an object of the invention to provide an integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that that makes it possible to keep the time required, in particular, for test operation of the memory comparatively low.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated memory, including memory cells disposed in at least first and second memory cell blocks, read amplifiers, data lines respectively connected to the read amplifiers, writable register circuits to be written from outside the memory, each of the memory cells respectively read out through one of the read amplifiers and one of the data lines connected to the one read amplifier, at least a dedicated one of the data lines being associated with each of the memory cell blocks for reading data from the memory cell blocks, at least a dedicated one of the register circuits being associated with each of the memory cell blocks, the register circuits adapted to store data and to compare the stored data with data applied to a respective one of the register circuits, and the dedicated one of the register circuits associated with a given one of the memory cell blocks being connected to the dedicated one of the data lines associated with the given memory cell block, the dedicated one of the register circuits adapted to compare data read out of the given memory cell block with the data stored in the dedicated one of the register circuits.
In the memory according to the invention, the time required for test operation of the memory is reduced by a plurality of memory banks and/or their read amplifiers being activated in parallel for a read access in multi-bank operation, as it is referred. The activation is made possible by the memory according to the invention because the memory has a plurality of writable register circuits to be written from outside the memory to store data (reference data) and to compare the stored data with applied test data. At the beginning of a test operation, the reference data is applied to the respective register circuit and stored therein. In such a case, each memory cell block is assigned at least one dedicated register circuit. To read the test data, for each memory cell block, the associated register circuit is connected to the associated data line so that a comparison between data to be read out from the respective memory cell block and the data stored in the associated register circuit can be carried out.
A memory cell access to read data stored in individual memory cells or in groups of memory cells is in this case carried out in an access cycle. During an access cycle, in each of the memory cell blocks, a respective memory cell or a group of memory cells is selected and respective read amplifiers are activated to read data to be read out. This means that, for the case in which a memory cell block corresponds to a memory bank, a so-called multi-bank operation is carried out, in which a plurality of memory banks, for example, belonging to a DRAM memory, are activated and read out in parallel. During an access cycle, the data read out is in each case compared with the reference data in parallel in the respective register circuits. A comparison result from a register circuit is, for example, output in the form of a pass/fail result, as it is referred. In such a case, a statement is made as to whether the test data agrees with the reference data or does not agree, from which statement it is possible to draw conclusions about the presence of a fault in the relevant memory cell block. These comparison results from the register circuits can either be output directly on corresponding data lines or, as an alternative thereto, can also firstly be logically linked with one another.
In such an embodiment of the invention, the register circuits respectively have an output for the output of a comparison result. The respective outputs of the register circuits can be connected to a combining circuit so that a combination of the comparison results at the outputs of the register circuits to form a resulting comparison result is carried out, by using which a test cycle of the entire memory can be assessed. If, for example, the comparison results from all the register circuits, and, therefore, the test results of all the memory cell blocks, xe2x80x9cpassxe2x80x9d, then such a test cycle is judged to have passed. If at least one of the register circuits outputs a xe2x80x9cfailxe2x80x9d result, which means that the test data in at least one memory cell block does not correspond to the reference data, then such a test cycle is judged not to have passed.
In accordance with another feature of the invention, each of the memory cell blocks is associated with at least two of the register circuits and, for a respective one of the memory cell blocks, a first circuit of the register circuits and a second circuit of the register circuits store mutually inverted data.
With the objects of the invention in view, there is also provided a method of operating an integrated memory, including the steps of organizing memory cells into at least first and second memory cell blocks, respectively connecting data lines to read amplifiers, respectively reading out each of the memory cells through one of the read amplifiers and one of the data lines connected thereto, dedicating at least one of the data lines with each of the memory cell blocks for reading data therefrom, dedicating at least one writable register circuit to be written from outside the memory with each of the memory cell blocks, the register circuits adapted to store data and to compare the stored data with data applied to a respective one of the register circuits, connecting a dedicated one of the register circuits associated with a given one of the memory cell blocks to the dedicated data line associated with the given memory cell block, the dedicated one register circuit adapted to compare data read out of the given memory cell block with the data stored in the dedicated one register circuit, carrying out a memory cell access in an access cycle to read an item of data stored in a memory cell, at a start of a test operation section, storing data in the register circuits of the respective memory cell blocks as reference data, and during an access cycle, in each of the memory cell blocks, selecting at least one of a respective memory cell and a group of memory cells and activating a respective read amplifier to read data to be read out and respectively carrying out a comparison between the data read out and the reference data in each of the register circuits.
With the objects of the invention in view, the method of operating an integrated memory includes the steps of, during an access cycle, in each of the memory cell blocks, selecting at least one memory cell and activating a respective read amplifier to read out data and respectively carrying out a comparison between the data read out and the reference data in each of the register circuits.
In accordance with a concomitant mode of the invention, the memory cell blocks of the memory and/or their read amplifiers are activated with a time offset from one another during an access cycle. Such a process advantageously achieves the situation where a current demand produced by the activation is distributed over a certain time interval so that no brief and comparatively large voltage dip in the supply voltage is produced. Accordingly, in principle, any desired number of independent memory cell blocks or memory banks can be activated in a manner staggered over time. However, because the respective read amplifiers are, so to speak, activated in parallel in an access cycle to assess the respective data signals, the time required for a memory cell access, in particular, during test operation, can be kept comparatively low.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.